Multithreaded microprocessor with register allocation based on number of active threads

ABSTRACT

A mechanism in a multithreaded processor to allocate resources based on configuration information indicating how many threads are in use.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a continuation application and claims priority toU.S. application Ser. No. 10/212,945, filed on Aug. 5, 2002, which inturn claims priority from U.S. Provisional Patent Application Ser. No.60/315,144, filed Aug. 27, 2001. The contents of these applications areincorporated herein in their entirety.

BACKGROUND

Typically, hardware implementations of multithreaded microprocessorsprovide for use by each thread a fixed number of resources, such asregisters, program counters, and so forth. Depending on the amount ofparallelism in an application program executing on the microprocessor,some of the threads may not be used. Consequently, the resources of theunused threads and, more specifically, the power and silicon areaconsumed by those resources, are wasted.

DESCRIPTION OF DRAWINGS

FIG. 1 shows a block diagram of a communication system employing aprocessor having multithreaded microengines to support multiple threadsof execution.

FIG. 2 shows a block diagram of the microengine (of FIG. 1).

FIG. 3 shows a microengine Control and Status Register (CSR) used toselect a number of “in use” threads.

FIG. 4 shows a schematic diagram of a dual-bank implementation of aGeneral Purpose Registers (GPR) file (of the microengine of FIG. 2) thatuses a selected number of “in use” threads to allocate registers tothreads.

FIG. 5 shows a table of thread GPR allocations for eight “in use”threads and four “in use” threads.

FIGS. 6A and 6B show the partition of registers in the GPR file inaccordance with the thread GPR allocations for eight “in use” threadsand four “in use” threads, respectively.

DETAILED DESCRIPTION

Referring to FIG. 1, a communication system 10 includes a processor 12coupled to one or more I/O devices, for example, network devices 14 and16, as well as a memory system 18. The processor 12 is multi-threadedprocessor and, as such, is especially useful for tasks that can bebroken into parallel subtasks or functions. In one embodiment, as shownin the figure, the processor 12 includes multiple microengines 20, eachwith multiple hardware controlled program threads 22 that can besimultaneously active and independently work on a task. In the exampleshown, there are “n” microengines 20, and each of the microengines 20 iscapable of processing multiple program threads 22, as will be describedmore fully below. In the described embodiment, the maximum number “N” ofcontext threads supported is eight, but other maximum amount could beprovided. Preferably, each of the microengines 20 is connected to andcan communicate with adjacent microengines.

The processor 12 also includes a processor 24 that assists in loadingmicrocode control for other resources of the processor 12 and performsother general-purpose computer type functions such as handling protocolsand exceptions. In network processing applications, the processor 24 canalso provide support for higher layer network processing tasks thatcannot be handled by the microengines 20. In one embodiment, theprocessor 24 is a StrongARM (ARM is a trademark of ARM Limited, UnitedKingdom) core based architecture. The processor (or core) 24 has anoperating system through which the processor 24 can call functions tooperate on the microengines 20. The processor 24 can use any supportedoperating system, preferably a real-time operating system. Otherprocessor architectures may be used.

The microengines 20 each operate with shared resources including thememory system 18, a PCI bus interface 26, an I/O interface 28, a hashunit 30 and a scratchpad memory 32. The PCI bus interface 26 provides aninterface to a PCI bus (not shown). The I/O interface 28 is responsiblefor controlling and interfacing the processor 12 to the network devices14, 16. The memory system 18 includes a Dynamic Random Access Memory(DRAM) 34, which is accessed using a DRAM controller 36 and a StaticRandom Access Memory (SRAM) 38, which is accessed using an SRAMcontroller 40. Although not shown, the processor 12 also would include anonvolatile memory to support boot operations. The DRAM 34 and DRAMcontroller 36 are typically used for processing large volumes of data,e.g., processing of payloads from network packets. In a networkingimplementation, the SRAM 38 and SRAM controller 40 are used for lowlatency, fast access tasks, e.g., accessing look-up tables, memory forthe processor 24, and so forth. The microengines 20 can execute memoryreference instructions to either the DRAM controller 36 or the SRAMcontroller 40.

The devices 14 and 16 can be any network devices capable of transmittingand/or receiving network traffic data, such as framing/MAC devices,e.g., for connecting to 10/100BaseT Ethernet, Gigabit Ethernet, ATM orother types of networks, or devices for connecting to a switch fabric.For example, in one arrangement, the network device 14 could be anEthernet MAC device (connected to an Ethernet network, not shown) thattransmits packet data to the processor 12 and device 16 could be aswitch fabric device that receives processed packet data from processor12 for transmission onto a switch fabric. In such an implementation,that is, when handling traffic to be sent to a switch fabric, theprocessor 12 would be acting as an ingress network processor.Alternatively, the processor 12 could operate as an egress networkprocessor, handling traffic that is received from a switch fabric (viadevice 16) and destined for another network device such as networkdevice 14, or network coupled to such device. Although the processor 12can operate in a standalone mode, supporting both traffic directions, itwill be understood that, to achieve higher performance, it may bedesirable to use two dedicated processors, one as an ingress processorand the other as an egress processor. The two dedicated processors wouldeach be coupled to the devices 14 and 16. In addition, each networkdevice 14, 16 can include a plurality of ports to be serviced by theprocessor 12. The I/O interface 28 therefore supports one or more typesof interfaces, such as an interface for packet and cell transfer betweena PHY device and a higher protocol layer (e.g., link layer), or aninterface between a traffic manager and a switch fabric for AsynchronousTransfer Mode (ATM), Internet Protocol (IP), Ethernet, and similar datacommunications applications. The I/O interface 28 includes separatereceive and transmit blocks, each being separately configurable for aparticular interface supported by the processor 12.

Other devices, such as a host computer and/or PCI peripherals (notshown), which may be coupled to a PCI bus controlled by the PC interface26 are also serviced by the processor 12.

In general, as a network processor, the processor 12 can interface toany type of communication device or interface that receives/sends largeamounts of data. The processor 12 functioning as a network processorcould receive units of packet data from a network device like networkdevice 14 and process those units of packet data in a parallel manner,as will be described. The unit of packet data could include an entirenetwork packet (e.g., Ethernet packet) or a portion of such a packet,e.g., a cell or packet segment.

Each of the functional units of the processor 12 is coupled to aninternal bus structure 42. Memory busses 44 a, 44 b couple the memorycontrollers 36 and 40, respectively, to respective memory units DRAM 34and SRAM 38 of the memory system 18. The I/O Interface 28 is coupled tothe devices 14 and 16 via separate I/O bus lines 46 a and 46 b,respectively.

Referring to FIG. 2, an exemplary one of the microengines 20 is shown.The microengine (ME) 20 includes a control unit 50 that includes acontrol store 51, control logic (or microcontroller) 52 and a contextarbiter/event logic 53. The control store 51 is used to store amicroprogram. The microprogram is loadable by the processor 24.

The microcontroller 52 includes an instruction decoder and programcounter units for each of supported threads. The The contextarbiter/event logic 53 receives messages (e.g., SRAM event response)from each one of the share resources, e.g., SRAM 38, DRAM 34, orprocessor core 24, and so forth. These messages provides information onwhether a requested function has completed.

The context arbiter/event logic 53 has arbitration for the eightthreads. In one embodiment, the arbitration is a round robin mechanism.However, other arbitration techniques, such as priority queuing orweighted fair queuing, could be used.

The microengine 20 also includes an execution datapath 54 and a generalpurpose register (GPR) file unit 56 that is coupled to the control unit50. The datapath 54 includes several datapath elements, e.g., and asshown, a first datapath element 58, a second datapath element 59 and athird datapath element 60. The datapath elements can include, forexample, an ALU and a multiplier. The GPR file unit 56 provides operandsto the various datapath elements. The registers of the GPR file unit 56are read and written exclusively under program control. GPRs, when usedas a source in an instruction, supply operands to the datapath 54. Whenuse as a destination in an instruction, they are written with the resultof the datapath 54. The instruction specifies the register number of thespecific GPRs that are selected for a source or destination. Opcode bitsin the instruction provided by the control unit 50 select which datapathelement is to perform the operation defined by the instruction.

The microengine 20 further includes a write transfer register file 62and a read transfer register file 64. The write transfer register file62 stores data to be written to a resource external to the microengine(for example, the DRAM memory or SRAM memory). The read transferregister file 64 is used for storing return data from a resourceexternal to the microengine 20. Subsequent to or concurrent with thedata arrival, event signals 65 from the respective shared resource,e.g., memory controllers 36, 40, or core 24, can be provided to alertthe thread that requested the data that the data is available or hasbeen sent. Both of the transfer register files 62, 64 are connected tothe datapath 54, the GPR file unit 56, as well as the control unit 50.

Also included in the microengine 20 is a local memory 66. The localmemory 66, which is addressed by registers 68 a, 68 b, also suppliesoperands to the datapath 54. The local memory 66 receives results fromthe datapath 54 as a destination. The microengine 20 also includes localcontrol and status registers (CSRs) 70 for storing local inter-threadand global event signaling information, as well as other information,and a CRC unit 72, coupled to the transfer registers, which operates inparallel with the execution datapath 54 and performs CRC computationsfor ATM cells. The local CSRs 70 and the CRC unit 72 are coupled to thetransfer registers, the datapath 54 and the GPR file unit 56.

In addition to providing an output to the write transfer unit 62, thedatapath 54 can also provide an output to the GPR file 56 over line 80.Thus, each of the datapath elements can return a result value from anexecuted.

The functionality of the microengine threads 22 is determined bymicrocode loaded (via the core processor 24) for a particular user'sapplication into each microengine's control store 51. For example, inone exemplary thread task assignment, one thread is assigned to serve asa receive scheduler thread and another as a transmit scheduler thread, aplurality of threads are configured as receive processing threads andtransmit processing threads, and other thread task assignments include atransmit arbiter and one or more core communication threads. Oncelaunched, a thread performs its function independently.

Referring to FIG. 3, the CSRs 70 include a context enable register(“CTX_Enable”) 90, which includes an “in use” contexts field 92 toindicate a pre-selected number of threads or contexts in use. The “inuse” contexts field 92 stores a single bit, which when cleared (X=0)indicates all of the 8 available threads are in use, and which when set(X=1) indicates that only a predefined number, e.g., 4, morespecifically, threads 0, 2, 4 and 6, are in use.

As shown in FIG. 4, the GPRs of the GPR file unit 56 may be physicallyand logically contained in two banks, an A bank 56 a and a B bank 56 b.The GPRs in both banks include a data portion 100 and an address portion102. Coupled to each register address path 102 is a multiplexor 104,which receives as inputs a thread number 104 and register number 106(from the instruction) from the control unit 50. The output of themultiplexor 104, that is, the form of the “address” provided to theaddress path 102 to select one of the registers 109, is controlled by anenable signal 110. The state of the enable signal 110 is determined bythe setting of the “In_Use” Contexts bit in the field 92 of theCTX_Enable register 90.

Conventionally, each thread has a fixed percentage of the registersallocated to it, for example, one-eighth for the case of eight threadssupported. If some threads are not used, the registers dedicated for useby those unused threads go unused as well.

In contrast, the use of the multiplexor 104 controlled by “in use”contexts configuration information in the CTX_Enable CSR 90 enables are-partitioning of the number of bits of active threadnumber/instruction (register number) bits in the register address andtherefore a re-allocation of registers to threads. More specifically,when the bit in field 92 is equal to a “0”, the number of “in use”threads is 8, and the enable 110 controls the multiplexor 104 to selectall of the bits of the active thread number 106 and all but the mostsignificant bit from the register number 108 specified by the currentinstruction. Conversely, when the bit in field 92 is set to a “1”, thenumber of “in use” threads is reduced by half, and the number ofregisters available for allocation is redistributed so that the numberof registers allocated per thread is doubled.

FIG. 5 shows the thread allocation for a register file of 32 registers.For 8 threads, thread numbers 0 through 7, each thread is allocated atotal of four registers. For 4 threads, thread numbers 0, 2, 4 and 6,each thread is allocated a total of eight registers.

FIGS. 6A and 6B show a register file (single bank, for example, registerfile 56 a) having 32 registers available for thread allocation andre-allocation among a maximum of eight supported threads. In an 8-threadconfiguration 120, that is, the case of eight threads in use, shown inFIG. 6A, each of the threads is allocated four registers. Themultiplexor 104 selects all three bits of the binary representation ofthe thread number and all bits except the most significant bit (that is,selects two bits (bits 0 and 1)) of the binary representation of theregister number from the instruction because the enable 110 is low. Fora 4-thread configuration 122, that is, when enable 110 is high and thusfour threads, as illustrated in FIG. 6B, each of the four threads isallocated eight registers. The multiplexer 104 selects all but the leastsignificant bit (in this case, selects two bits, bits 1 and 2) of thebinary representation of the thread number and selects all three bits(bits 0-2) of the binary representation of the register number from theinstruction. Thus, the address into the register file is a concatenationof bits of the currently active thread number with bits of the registernumber from the instruction, and the contributing number of bits fromeach is determined by the setting of the In_Use contexts bit 92 in theCTX_Enable register 90 (from FIG. 3).

Thus, the GPRs are logically subdivided in equal regions such that eachcontext has relative access to one of the regions. The number of regionsis configured in the In_Use contexts field 92, and can be either 4 or 8.Thus, a context-relative register number is actually associated withmultiple different physical registers. The actual register to beaccessed is determined by the context making the access request, thatis, the context number concatenated with the register number, in themanner described above. Context-relative addressing is a powerfulfeature that enables eight or four different threads to share the samecode image, yet maintain separate data. Thus, instructions specify thecontext-relative address (register number). For eight active contexts,the instruction always specifies registers in the range of 0-3. For fouractive contexts, the instruction always specifies registers in the rangeof 0-7.

Referring back to the table shown in FIG. 4, the absolute GPR registernumber is the register number that is actually used by the registeraddress path (decode logic) to access the specific context-relativeregister. For example, with 8 active contexts, context-relative thread 0for context (or thread) 2 is 8.

The above thread GPR allocation scheme can be extended to differentnumbers of threads (based on multiples of 2) and registers, for example,re-allocating a total of 128 registers from among a maximum number of 8“in use” threads (16 registers each) to 4 “in use” threads (32 registerseach), or re-allocating a total of 128 registers from among a maximumnumber of 16 “in use” threads (8 registers each) to 8 “in use” threads(16 registers each).

Other embodiments are within the scope of the following claims.

1. A method of allocating resources in a multithreaded processorcomprising: providing resources for use by execution threads supportedby the multithreaded processor; and applying configuration informationto a selection of the resources to allocate the resources among activeones of the execution threads.
 2. The method of claim 1 wherein theresources comprise: registers in a general purpose register file.
 3. Themethod of claim 1 wherein the configuration information comprises: aconfiguration bit which when cleared indicates all of the supportedexecution threads as the active ones and when set indicates a portion ofthe supported execution threads as the active ones.
 4. The method ofclaim 1 wherein the configuration information comprises: a configurationbit which when cleared indicates all of the supported execution threadsas the active ones and when set indicates half of the supportedexecution threads as the active ones.
 5. The method of claim 3, whereinthe configuration bit resides in a control and status register.
 6. Themethod of claim 2 wherein the general purpose register file includes anaddress decode portion and a multiplexor coupled to the address decodeportion, the multiplexor to receive a thread number and a registernumber as inputs and to select bits of the thread number and theregister number based on the configuration information to form anaddress corresponding to one of the registers.
 7. The method of claim 6wherein the configuration information indicates selection of all but theleast signification bit of the thread number and all bits of theregister number.
 8. The method of claim 6 wherein the configurationinformation indicates selection of all but the most significant bit ofthe register number and all bits of the thread number.
 9. The method ofclaim 6 wherein the selected bits of the register number form athread-relative register number.
 10. A processor comprising: resourcesfor use by execution threads supported by the processor; and a resourceselector to receive configuration information and to allocate theresources among active ones of the execution threads based on theconfiguration information.
 11. The processor of claim 10 wherein theresources comprise: registers in a general purpose register file. 12.The processor of claim 10 wherein the configuration informationcomprises: a configuration bit which when cleared indicates all of thesupported execution threads as the active ones and when set indicates aportion of the supported execution threads as the active ones.
 13. Theprocessor of claim 10 wherein the configuration information comprises: aconfiguration bit which when cleared indicates all of the supportedexecution threads as the active ones and when set indicates half of thesupported execution threads as the active ones.
 14. The processor ofclaim 12, wherein the configuration bit resides in a control and statusregister.
 15. The processor of claim 11 wherein the general purposeregister file includes an address decode portion and the resourceselector is a multiplexor coupled to the address decode portion, themultiplexor to receive a thread number and a register number as inputsand to select bits of the thread number and the register number based onthe configuration information to form an address corresponding to one ofthe registers.
 16. The processor of claim 15 wherein the configurationinformation indicates selection of all but the least signification bitof the thread number and all bits of the register number.
 17. Theprocessor of claim 15 wherein the configuration information indicatesselection of all but the most significant bit of the register number andall bits of the thread number.
 18. The processor of claim 15 wherein theselected bits of the register number form a thread-relative registernumber.